Learn System Verilog Through Examples - 1: Use of enum

Examples always help to understand the concept, especially end to end cases that one can go through. Let's start with the first example on the enum. In the below example especially note the casting command...

typedef enum {RED,BLUE,GREEN} COLOR;

enum {MON,TUE=5,WED} DAY;

module test;

  string message = "Hello !";

  COLOR in_color,out_color;

                initial begin

      DAY = TUE;

      $display("OUT1: %s",message);

      $display("OUT2: %s",in_color.name);

      $display("OUT3: %d",DAY);

      in_color++;

      out_color = in_color;

      $display("OUT4: %s %d",out_color.name,out_color);

      //Following assignment is wrong

      //COMPILER ERROR: Assignment to enum variable from expression of different type.

      //in_color = 2;

      $cast(in_color,2);

      $display("OUT5: %s",in_color.name);

    end

endmodule

# KERNEL: OUT1: Hello !

# KERNEL: OUT2: RED

# KERNEL: OUT3:           5

# KERNEL: OUT4: BLUE           1

# KERNEL: OUT5: GREEN